1. Field of the Invention
The present invention relates to phase locked loop (PLL) and a motor controller that makes use of it, in particular to a PLL motor controller for controlling the speed of the motor by the use of digital PLL.
2. Description of the Prior Art
As a PLL motor controller of the above kind, there has been known in the past, for example, a PLL phase detector (commercial name: MC-4044) made by Motorola Corp. in the United States, as shown in FIG. 1. This device is constructed as follows. Namely, the device receives a clock with reference frequency (referred to as the reference pulse hereafter) that corresponds to the speed of the motor rotation that is to be set and a clock with timing that corresponds to the rotation speed of the motor (referred to as FG pulse hereafter) in the terminals R and V, respectively. Then, two error signals that have waveforms of a kind of pulse width modulated (PWM), are output from terminals U and D of the device and are converted to an analog quantity by a charge pump. The signals are smoothed next by an integrator to be sent out to a motor driving system.
In such a configuration, an error signal that is analog-converted is added with a loop delay which is introduced due to the constants C and R that exist in the charge pump or the integrator. Because of this, when the motor is lightly loaded or has a low inertia, in particular, it has been difficult to control the motor with satisfactory response to the rotation speed to be set and also it has been difficult to control the gain of the phase to voltage ratio (P/V ratio).
Moreover, if there are included constants C and R in the PLL circuit, then that PLL circuit is not suited for a monolithic integration of the circuit.